tb_processor.cc
// INCLUDE THE CLASS DECLARATION
#include "tb_processor.h"
// INCLUDE THE REGISTER SET
#include "cos.h"
//*******************************
// CLASS DEFINITION: TB_Processor
//*******************************
// CONSTRUCTOR
TB_Processor::TB_Processor(const string& name, TB_Values& adc, TB_Values& dac):
Processor(name), d_adc(adc), d_dac(dac)
{}
// DESTRUCTOR
TB_Processor::~TB_Processor()
{}
// METHOD: interrupt()
void
TB_Processor::interrupt()
{
// READ THE TRANSMIT REGISTER
int tx_reg = in(COS::Transmit);
// IF THE TRANSMIT CHANNEL IS GENERATING AN INTERRUPT
if ((COS::IruptMask | COS::Interrupt) == ((COS::IruptMask | COS::Interrupt) & tx_reg))
{
// GET THE NUMBER OF FREE DATA WORDS IN THE TRANSMIT FIFO
int size = tx_reg & COS::Size;
// FOREACH FREE DATA WORD AND PROVIDED THE STORE HAS DATA
for (int icnt=0; icnt<size && d_dac.has_value(); ++icnt)
// READ STORE THEN WRITE DATA TO THE TRANSMIT FIFO
out(COS::Data, d_dac.get_value());
// IF THERE IS NO MORE DATA TO WRITE, DISABLE CHANNEL INTERRUPTS
if (!d_dac.has_value())
out(COS::Transmit, tx_reg & ~COS::IruptMask);
}
// READ THE RECEIVE REGISTER
int rx_reg = in(COS::Receive);
// IF THE RECEIVE CHANNEL IS GENERATING AN INTERRUPT
if ((COS::IruptMask | COS::Interrupt) == ((COS::IruptMask | COS::Interrupt) & rx_reg))
{
// GET THE NUMBER OF DATA WORDS IN THE RECEIVE FIFO
int size = rx_reg & COS::Size;
// FOREACH DATA WORD AND PROVIDED THE STORE HAS SPACE
for (int icnt=0; icnt<size && !d_adc.is_full(); ++icnt)
// READ THE RECEIVE FIFO THEN WRITE DATA TO THE STORE
d_adc.put_value(in(COS::Data));
// IF THERE IS NO MORE DATA TO READ, DISABLE CHANNEL INTERRUPTS
if (d_adc.is_full())
out(COS::Receive, rx_reg & ~COS::IruptMask);
}
}
© Copyright 2000-2001 Adrian Lewis