tb_codec_on_a_stick.v
module tb;
// INTERNAL SIGNALS
// GLOBAL CLOCK AND ACTIVE-LOW RESET
wire clock;
wire resetj;
// PROCESSOR BUS
wire [15:0] up_addr;
wire up_write;
wire up_read;
tri1 [15:0] up_data;
wire up_ready;
wire up_int;
// SERIAL CODEC BUS
wire sc_clock;
wire sc_sync;
wire sc_tx;
wire sc_rx;
// IMPLEMENTATION
// GENERATE CLOCK AND RESET, HANDLE SIMULATION TERMINATION PROCEDURE
test_services ts (clock, resetj);
// 16 BIT PROCESSOR MODEL
processor #("processor", 16, 16) up (clock, up_int, up_read, up_write, up_addr, up_data, up_ready);
// SERIAL CODEC MODEL
codec #("codec") sc (sc_clock, sc_sync, sc_tx, sc_rx);
// DESIGN UNDER TEST
codec_on_a_stick asic
(
clock, resetj,
up_addr[15:2] == 'b0, up_addr[1:0], up_write, up_read, up_data, up_ready, up_int,
sc_clock, sc_sync, sc_tx, sc_rx
);
// LOG WAVEFORMS
initial
begin
$dumpfile("tb_codec_on_a_stick.dmp");
$dumpvars(0, tb);
end
endmodule
© Copyright 2000-2001 Adrian Lewis