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Practically all designs of any size contain or interface to some kind of memory. It is not uncommon for library or part suppliers to provide Verilog memory models of the memory cells and components they supply. However, although these memory models may function correctly, they often suffer from several shortcomings.
This section presents a simple memory model that has none of the drawbacks of Verilog memory models. This code can also be used to adapt memory models supplied by vendors, removing the Verilog memory and replacing it with an SMI model. This technique can be used to create memory models with the interface and timing specifications supplied by a vendor but with the flexibility and performance of an SMI memory model.
The hardware model presented in this section implements a synchronous single port SRAM. The data and address bus widths are programmable but only width of 32 bits or less are supported. Only binary values can be stored in the memory, writing 'X' or 'Z' to the memory will cause the software model to raise an exception. The memory operates on each positive "clock" edge provided the "resetj" signal is high. Each cycle, the "data_out" bus is set to the contents of the memory location corresponding to the value of the "address" bus. If the "write_enable" signal is high, the value of the "data_in" bus is written to the memory location corresponding to the value of the "address" bus.
Figure 3.1.1: Example SRAM Model
| SMI Model: | SRAM | |
|---|---|---|
| Parameter: | INSTANCE | SMI instance name. |
| SIZE | Sets the number of words stored by the memory model to 2^SIZE. | |
| WIDTH | The bit width of the words stored by the memory model. | |
| Clock Domains: | clock | All signals switch on posedge "clock" unless stated otherwise. |
| Inputs: | address[SIZE-1] | Address of the memory word to perform the memory operation on. |
| clock | Clock signal. | |
| resetj (asynchronous) | Active low reset signal. If zero, no memory operations are performed. | |
| write_enable | If this signal is set, a write operation is performed, else a read. | |
| data_in[WIDTH-1] | This data is written to the memory if a write operation is performed. | |
| Outputs: | data_out[WIDTH-1] | This output transmits data read from the memory if either a read or a write operation is performed. |
At start up, the hardware model instance is initialized then a "Configure" message is sent to the software model instance, specifying the bit width of the memory.
During simulation, the memory operates each clock cycle (posedge clock) provided that reset is not asserted (resetj != 0). If the "write_enable" signal is low, a read operation is performed by sending a "Read" message to the software model instance. This message contains the value of the "address" bus, which is used to access the memory location corresponding to this value. The contents of this memory location are returned to the hardware model instance in a "Data" message. The memory value contained in the "Data" message is used to drive the "data_out" bus. If the "write_enable" signal is high, a read and a write operation are performed by sending a "Read+Write" message to the software model instance. This message contains the value of the "address" bus, which is used to access the memory location corresponding to this value. The message also contains the value of the "data_in" bus, which is the value written to the memory location after it's present value has been returned in a "Data" message. The memory value contained in the "Data" message is used to drive the "data_out" bus.
ON posedge clock AND IF resetj != 0 IF write_enable == 0: data_out = memory[address] IF write_enable == 1: data_out = memory[address]; memory[address] = data_in
| Source: | SRAM.v |
|---|
| Name | Type | Content | Reply |
|---|---|---|---|
| Configure | HS-W | [MEM_CONFIG, <width>] | |
| Read | HS-R | [MEM_READ, <address>] | Data |
| Read+Write | HS-R | [MEM_WRITE, <address> <data>] | Data |
| Data | SM-R | [<data>] |
Constants "MEM_CONFIG", "MEM_READ" and "MEM_WRITE" are used to identify the three different types of message, "Configure", "Read+Write" and "Read", that can be sent from the hardware to the software model instance. After each hardware model instance initializes it sends a "Configure" message to the software model instance, specifying the bit width of the memory. The hardware model instance then sends either a "Read+Write" or a "Read" message each clock cycle, provided the memory is not in reset. The software model instance replies with a "Data" message.
| Message: | Configure | |
|---|---|---|
| Content: | width | Bit width of the memory. |
| Description: | This message is sent once, at simulation start-up, before either of the other message types have been sent. The message contains the word width of the memory. | |
| Message: | Read | |
|---|---|---|
| Content: | address | Address of the memory word to be read. |
| Reply: | Data | Value of the word stored at the memory location indicated by the address. |
| Description: | This message is used to read a data word from a given address in the memory. | |
| Message: | Read+Write | |
|---|---|---|
| Content: | address | Address of the memory word to read and write. |
| data | Value to be stored in the memory location indicated by the address. | |
| Reply: | Data | Value of the word previously stored at the memory location indicated by the address. |
| Description: | This message is used to write a data word to a given address in the memory. The value being overwritten is returned in the reply message. | |
| Message: | Data | |
|---|---|---|
| Content: | data | Value read from the memory location indicated operation causing this message to be transmitted. |
| Description: | This reply message returns data read from the memory back to the hardware simulation. | |
Figure 3.1.3: An example SRAM class
This class implements a very simple SMI model of an SRAM. The model name is "SRAM" the instance name is passed to the constructor. The memory model stores words made up of binary bits ('x' and 'z' are not allowed). The word width is fixed per model instance and configured from the hardware model instance. The maximum word width supported is 32 bits. The address width is also limited to a maximum of 32 bits.
The memory storage is implemented using a map class from the Standard Template Library (STL). The address and data are stored as pairs keyed by the address value. This implementation is best suited to applications that require large sparse memories, i.e. memories that support large address ranges though only a small subset of available memory locations are actually used.
In addition to implementing a memory model, the software model provides an interface to the test process. The test process can query the word width configured by the hardware model instance using the queryWidth() method. The test process can read from and write to the memory using the getData() and setData() methods respectively. These methods allow the memory to be initialized prior to use, dumped after the test has completed, and accessed dynamically during the simulation.
| Source: | SRAM.h |
|---|---|
| SRAM.cc |
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