processor.h
// INCLUDE THE SMI MODEL BASE CLASS DECLARATION
#include "smi_model.h"
// DECLARE CLASSES USED IN THE INTERFACE
#include <string>
class SMI_TxMessage;
class SMI_RxMessage;
class Processor:
public SMI_Model
{
public:
// CONSTRUCTOR
//
// ARGUMENT: name
// SMI instance name.
//
// DESCRIPTION:
// Constructs new software model instance of a Processor model. Registers
// the model with SMI with SMI model name "processor" and the SMI instance
// name passed by argument.
Processor(const string& name);
// DESTRUCTOR
virtual ~Processor();
// METHOD: idle()
//
// DESCRIPTION:
// Issue an "idle" instruction which causes a single inactive bus cycle.
void idle();
// METHOD: out(address, data)
//
// ARGUMENT: address
// Address written to by the bus write operation.
//
// ARGUMENT: data
// Data written to the address by the bus write operation.
//
// DESCRIPTION:
// This method instructs the processor hardware model to perform a bus
// write operation. The model will perform the sequence of signal
// transitions necessary to write data to the address specified by the
// message contents.
void out(unsigned long address, unsigned long data);
// METHOD: in(address)
//
// ARGUMENT: address
// Address read by the bus read operation.
//
// RETURNS:
// Returns the data read by the bus read operation.
//
// DESCRIPTION:
// This method instructs the processor hardware model to perform a bus
// read operation. The model will perform the sequence of signal
// transitions necessary to read data from the address specified by the
// message contents. The data read is returned.
unsigned long in(unsigned long address);
// METHOD: interrupt()
//
// DESCRIPTION:
// This virtual method is supplied by the model user to provide interrupt
// handling. The method should invoke processor instructions that disable
// the source of the interrupt. When the interrupt service routine ends
// interrupt servicing is re-enabled and this routine will be called again
// if further interrupts are encountered. By default, the interrupt
// service does nothing.
virtual void interrupt() {};
private:
// CONSTANT: USED TO IDENTIFY THE MESSAGE TYPE
static const unsigned int CPU_NULL;
static const unsigned int CPU_CONFIGURE;
static const unsigned int CPU_INTERRUPT;
static const unsigned int CPU_INSTRUCTION;
static const unsigned int CPU_IRET;
static const unsigned int CPU_IDLE;
static const unsigned int CPU_IN;
static const unsigned int CPU_DATA;
static const unsigned int CPU_OUT;
// DATA: REPLY MESSAGE
SMI_TxMessage* d_instruction;
// DATA: BIT WIDTH OF THE ADDRESS BUS
unsigned long d_addr_width;
// DATA: BIT WIDTH OF THE DATA BUS
unsigned long d_data_width;
// DATA: MESSAGE IDENTIFIER RECEIVED FROM THE HARDWARE MODEL INSTANCE
unsigned long d_inbox;
// DATA: DATA VALUE FROM THE LAST Data MESSAGE
unsigned long d_return;
// METHOD: process(rx)
//
// ARGUMENT: rx
// Incoming message.
//
// RETURNS:
// Reply message.
//
// DESCRIPTION:
// Implements processor model operations by processing incoming messages.
SMI_TxMessage* process(const SMI_RxMessage& rx);
// METHOD: send()
//
// DESCRIPTION:
// Waits for an instruction message to be send to the hardware model
// instance. The method will process interrupt requests if they are
// received before an instruction request.
void send();
// METHOD: receive()
//
// RETURNS:
// Data read by the bus read operation.
//
// DESCRIPTION:
// Waits for the hardware model instance to reply to an "in" instruction
// by returning a Data message.
unsigned long receive();
// DISABLE DEFAULT CONSTRUCTORS
Processor();
Processor(const Processor&);
};
© Copyright 2000-2001 Adrian Lewis