codec_on_a_stick.v
module codec_on_a_stick
(
clock, resetj, up_pi_cs,
up_pi_addr, up_pi_write, up_pi_read, up_pi_data, pi_up_ready, pi_up_int,
ci_sc_clock, ci_sc_sync, ci_sc_data, sc_ci_data
);
// INTERFACE
input clock;
input resetj;
// PROCESSOR BUS
input up_pi_cs;
input [1:0] up_pi_addr;
input up_pi_write;
input up_pi_read;
inout [15:0] up_pi_data;
wire [15:0] pi_up_data;
output pi_up_ready;
output pi_up_int;
// SERIAL CODEC BUS
output ci_sc_clock;
output ci_sc_sync;
output ci_sc_data;
input sc_ci_data;
// INTERNAL SIGNALS
// PROCESSOR INTERFACE <=> TRANSMIT FIFO
wire pi_tf_write;
wire [15:0] pi_tf_data;
wire [6:0] tf_pi_size;
wire tf_pi_ready;
// PROCESSOR INTERFACE <=> RECEIVE FIFO
wire pi_rf_read;
wire [15:0] rf_pi_data;
wire [6:0] rf_pi_size;
wire rf_pi_ready;
// CODEC INTERFACE <=> TRANSMIT FIFO
wire ci_tf_read;
wire [15:0] tf_ci_data;
// CODEC INTERFACE => RECEIVE FIFO
wire ci_rf_write;
wire [15:0] ci_rf_data;
// PROCESSOR INTERFACE => CODEC INTERFACE
wire [1:0] pi_ci_enable;
// IMPLEMENTATION
// DRIVE DATA BUS WHEN RESPONDING TO A READ CYCLE
assign up_pi_data = up_pi_cs && up_pi_read && pi_up_ready ?
pi_up_data : 16'bz;
processor_interface pi
(
clock, resetj,
up_pi_cs, up_pi_addr, up_pi_write, up_pi_read,
up_pi_data, pi_up_data, pi_up_ready, pi_up_int,
pi_tf_write, pi_tf_data, tf_pi_size, tf_pi_ready,
pi_rf_read, rf_pi_data, rf_pi_size, rf_pi_ready,
pi_ci_enable
);
transmit_fifo #(6, 16) tf
(
clock, resetj,
pi_tf_write, pi_tf_data, tf_pi_size, tf_pi_ready,
ci_tf_read, tf_ci_data
);
receive_fifo #(6, 16) rf
(
clock, resetj,
pi_rf_read, rf_pi_data, rf_pi_size, rf_pi_ready,
ci_rf_write, ci_rf_data
);
codec_interface ci
(
clock, resetj,
pi_ci_enable,
ci_tf_read, tf_ci_data,
ci_rf_write, ci_rf_data,
ci_sc_clock, ci_sc_sync, ci_sc_data, sc_ci_data
);
endmodule
© Copyright 2000-2001 Adrian Lewis