test_services.v
module test_services (clock, resetj);
// PARAMETERS
// CLOCK PERIOD AND RESET DURATION
parameter HALF_PERIOD = 500;
parameter RESET_TIME = 2000;
// INTERFACE
output clock;
output resetj;
// INTERNAL SIGNALS
// CLOCK AND ACTIVE LOW RESET
reg clk;
reg rstj;
// SIMULATION EXIT FLAG
integer is_exiting;
// IMPLEMENTATION
// GENERATE CLOCK
always
if (clk) clk = #HALF_PERIOD 0;
else clk = #HALF_PERIOD 1;
// GENERATE RESET
initial
begin
// HANDLE CONTROL-C
$smi_signal;
// GENERATE RESET
rstj = 0;
rstj <= #RESET_TIME 1;
end
// POLL SIMULATION EXIT FLAG EACH CLOCK CYCLE
always@(posedge clk)
begin
// POLL SIMULATION EXIT FLAG
is_exiting = 0;
$smi_poll_exiting(is_exiting);
// IF SIMULATION EXIT REQUESTED
if (is_exiting == 1)
begin
// SIMULATION EXIT PROCEDURE
$display("test_services: exiting");
// FLUSH WAVEFORM LOG
$dumpflush;
// SHUTDOWN SMI MODELS/PROCESSES
$smi_finish;
// EXIT THE SIMULATION
$finish;
end
end
// CONNECT OUTPUTS
assign clock = clk;
assign resetj = rstj;
endmodule
© Copyright 2000-2001 Adrian Lewis