codec_interface.v
module codec_interface
(
    clock, resetj,
    pi_ci_enable,
    ci_tf_read, tf_ci_data,
    ci_rf_write, ci_rf_data,
    ci_sc_clock, ci_sc_sync, ci_sc_data, sc_ci_data
);

// INTERFACE
    
    input clock;
    input resetj;
    
    // CHANNEL CONTROL BUS
    
    input [1:0] pi_ci_enable;
    
    // TRANSMIT FIFO INTERFACE
    
    output        ci_tf_read;
    input  [15:0] tf_ci_data;
    
    // RECEIVE FIFO INTERFACE
    
    output        ci_rf_write;
    output [15:0] ci_rf_data;
    
    // SERIAL CODEC BUS
    
    output ci_sc_clock;
    output ci_sc_sync;
    output ci_sc_data;
    input  sc_ci_data;
    
// INTERNAL SIGNALS

    // SERIAL BIT COUNT 16 DOWN TO 0, SYNC (16) PLUS 16 DATA BITS (15-0)

    reg [4:0] bit_count;

    // DATA FROM THE TRANSMIT FIFO

    reg [15:0] tf_data;

    // DATA FOR THE RECEIVE FIFO

    reg [15:0] rf_data;

    // DATA BIT TRANSMITTED ON THE SERIAL CODEC BUS

    reg sc_data;

    // SAMPLED RECEIVE ENABLE

    reg rf_active;

// IMPLEMENTATION

    always@(posedge clock or negedge resetj)

        // IF RESET ACTIVE, RESET REGISTERS

        if (!resetj)
        begin
            bit_count <= 16;
            tf_data <= 0;
            rf_data <= 0;
            rf_active <= 0;
        end

        // ELSE 

        else
        begin
            // IF THIS IS THE SYNC CYCLE

            if (bit_count == 16)
            begin
                // SAVE THE TRANSMIT FIFO DATA (NOT NECESSARILY A READ)

                tf_data <= tf_ci_data;

                // SAMPLE THE RECEIVE ENABLE

                rf_active <= pi_ci_enable[1];
            end

            // ELSE STORE THE SERIAL BIT INPUT

            else
                rf_data[bit_count] <= sc_ci_data;

            // DECREMENT THE BIT COUNTER MOD 17

            if (bit_count == 0) bit_count <= 16;
            else bit_count <= bit_count - 1;
        end

    // SELECT THE SERIAL BIT OUTPUT

    always@(tf_data or bit_count)
        if (bit_count == 16) sc_data = 0;
        else sc_data = tf_data[bit_count];

    // ACKNOWLEDGE READING THE TRANSMIT FIFO IF ENABLED

    assign ci_tf_read  = bit_count == 5'd0  && pi_ci_enable[0];

    // WRITE TO THE RECEIVE FIFO IF ENABLED

    assign ci_rf_write = bit_count == 5'd16 && rf_active;
    assign ci_rf_data  = rf_data;

    // DRIVE THE SERIAL BUS AND PULSE SYNC IF RECEIVE OR TRANSMIT IS ENABLED

    assign ci_sc_data  = sc_data;
    assign ci_sc_sync  = bit_count == 5'd16 && |pi_ci_enable;
    assign ci_sc_clock = clock;

endmodule
© Copyright 2000-2001 Adrian Lewis