Fifofum Home Page

Features

• Fifofum provides an easy-to-use GUI but can also be integrated into an automatic build environment.
• Fifofum can generate a testbench and test your FIFO configuration.
• Builds synchronous FIFOs based on flip-flops, single or dual port memories.
• Builds asynchronous FIFOs based on flip-flops.
• FIFOs use a standard interface regardless of storage implementation.
• Optional outputs: full, empty, count, and space.
• Optional inputs: per-clock-domain synchronous reset for asynchronous FIFOs.
• Low-power option gates clock to all flop-based entries except the one being written.
• Open source: standard GNU License, no sign-up required, no special conditions of use!

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Why use Fifofum?

The choice of storage medium for FIFO entries depends on the FIFO size and access requirements. For FIFOs containing less than 1k bits, a flip-flop implementation is usually more efficient than a memory-based implementation; using a single-port memory rather than a dual-port memory saves area but halves the bandwidth available for data transfers. As design constraints often change during or after the initial design phase, having a consistant interface regardless of storage type is highly desirable; the FIFO size and type can be changed without having to change the logic that interfaces to the FIFO. Fifofum generates FIFOs that use a standard interface, which makes migrating between storage implementations transparent to the surrounding logic, aside from changes in timing characteristics.

Fifofum FIFOs also support lots of cool features - quite literally in the case of the low-power option. There are also lots of optional extras, but as the FIFOs are fully configurable, you only get the options you need.

FIFO specifications

Standard Interface

Both the read and write interfaces to Fifofum FIFOs are based on the same standard interface using the same protocol. The source data bus is qualified with a valid signal. The receiver asserts a ready signal when it is prepared to accept valid data. At the end of each clock cycle, data is transferred if both the valid and ready signals are asserted.

An important characteristic of this protocol is that FIFOs using this protocol may be connected in series without any additional glue logic. User logic using this protocol may also be connected in series to FIFOs or other similar logic.

Optional outputs

• wr_full is asserted if there are no unused FIFO entries.
• wr_space is the number of unused FIFO entries.
• rd_empty is asserted if there are no FIFO entries storing valid data.
• rd_count is the number of FIFO entries storing valid data.

Synchronous flip-flop based FIFOs

Fifofum generates flip-flop based FIFOs of any bit width and any depth. In general it is not possible to write to the FIFO when it is full, even if the FIFO is being read on the same cycle. For one-entry-deep FIFOs, it is possible to write when the FIFO is full provided that the FIFO is also being read; note that this feature creates a timing path between rd_ready and wr_ready.

FIFO entries are stored in arrays of flip-flops, either a simple Verilog memory or, in the low power configuration, an array of flop-flops per-FIFO-entry. Details of the low-power implementation are documented below.

Synchronous dual-port memory-based FIFOs

Fifofum generates dual-port memory-based FIFOs of any bit width and any depth. For mid-sized FIFOs, a FIFO based on a dual-port memory is more area efficient than a FIFO based on flip-flips, though it is important to take into account routing area to the memory and memory-BIST logic.

These FIFOs provide two additional interfaces for connection to the read and write ports of a user-provided dual-port memory. The write port interface contains three signals:

• wp_address is the address of the entry being written.
• When wp_write is asserted, data is written to the memory at the address provided.
• wp_data is the data being written to the memory.

• rp_address is the address of the entry being read.
• When rp_read is asserted, data is read from the memory at the address provided.
• On the clock cycle after rp_read is asserted, rp_data is the data read from the memory.

Synchronous single-port memory-based FIFOs

Fifofum generates single-port memory-based FIFOs of any bit width and any depth. For large FIFOs, a FIFO based on a single-port memory is more area efficient than a FIFO based on a dual-port memory, though it is important to understand the performance implications of this implementation. For FIFOs based on flip-flops and dual-port memories, it is possible to read and write simultaneously and continuously for as long as the user requires. FIFOs based on single-port memories have half the memory bandwidth of FIFOs base on a dual-port memory; simultaneous reads and writes are not possible. If both operations are requested on the same cycle, priority can either be given to the read or the write operation. Fifofum can generate single-port FIFOs with either read or write priority. Note that if the FIFO is configured with read-priority, a timing path exists between rd_ready and wr_ready.

These FIFOs provide an additional interface for connection to a user-provided single-port memory. The interface contains five signals:

• sp_address is the address of the entry being accessed.
• When sp_access is asserted, data is either read from or written to the memory at the address provided.
• When both wp_write and sp_access are asserted, data is written to the memory at the address provided.
• wp_data is the data being written to the memory.
• On the clock cycle after sp_access is asserted and wp_write is de-asserted, rp_data is the data read from the memory.

Asynchronous flip-flop based FIFOs

Fifofum generates asynchronous flip-flop-based FIFOs of any bit width. The depth of the asynchronous FIFOs must be 2 to the power of any positive, non-zero, integer, i.e. 2, 4, 8, etc. The read and write interfaces of these FIFOs can operate on two independent clock domains. All wr_* signals are synchronous to wr_clock; all rd_* signals are synchronous to rd_clock. There are no restrictions on the either clock frequency other than normal intra-domain timing constraints.

Both clock domains have their own asynchronous reset input (wr_reset_n and rd_reset_n) and should both be asserted during chip reset. However if your application requires support for reseting one rather than both clock domains, then asserting a single asynchronous reset may have an undesireable side-effect. If only one asynchronous reset is asserted, then an empty FIFO might appear to contain data after reset is de-asserted. Optional synchronous resets (wr_reset and rd_reset) allow reset in one domain to reset the FIFO pointer logic in both domains, and hence an empty FIFO will remain empty before and after reset.

The asynchronous FIFO maintains two gray-code counters, one in each domain. As both interfaces use the value of both counters, the value of each counter is double-synchronized for use by the other clock domain. The use of gray code ensures that the value captured by the receiving clock domain is either the current or next counter value as the value changes. The synchronous reset must also be passed to both domains to ensure that both counter are reset and that an empty FIFO remains empty throughout the reset operation. A double-synchronizer is used to avoid meta-stablity in the receiving clock domain.

FIFO entries are stored in arrays of flip-flops, either a simple Verilog memory or, in the low power configuration, an array of flop-flops per-FIFO-entry. Details of the low-power implementation are documented below.

Low-power clock gating

FIFO entries are stored in arrays of flip-flops, either a simple Verilog memory or, in the low power configuration, an array of flop-flops per-FIFO-entry. In the low-power configuration, the array of flip-flops for each entry has a gated clock which is only enabled when that entry is being written.

Low-power FIFOs have a scan_mode input; it is used to enable the gated-clock when scan testing is in progress.

The user can either provide the name of the clock-gate module or use the clock-gate module (fff_gate) provided by Fifofum. The user supplied module must support the inputs, outputs, and functionality of the Fifofum clock gate module, though the internal implementation is user defined.

• Inputs: in - the ungated clock; enable - the clock enable signal.
• Output: out - the gated clock.
• Functionality: out = in when enable is asserted, otherwise out holds its value regardless of the value of in.

Timing characteristics

Building FIFOs with Fifofum

Building FIFOs using the GUI

The GUI is divided into five vertically-stacked sections:

1. Name, dimensions, and interface
   • Module: the name of the verilog module implementing the FIFO.
   • Depth: the depth of the FIFO, i.e. the maximum number of entries that can be stored.
   • Width: the width of each FIFO entry in bits.
   • Outputs: include optional FIFO status outputs.
     • Full: wr_full is asserted if there are no unused FIFO entries.
     • Space: wr_space is the number of unused FIFO entries.
     • Empty: rd_empty is asserted if there are no FIFO entries storing valid data.
     • Count: rd_count is the number of FIFO entries storing valid data.
   • Sync-reset: Synchronous resets wr_reset and rd_reset allow reset in one domain to reset the FIFO pointer logic in both domains. This logic allows reset to be asserted from only one clock domain.
2. Storage and internal configuration
   • Flip-flops: select storage based on flip-flops. Options select between synchronous and asynchronous FIFO types; normal or low-power operation. The name of an externally defined clock gate can be specified, otherwise the fff_gate module will be defined and instantiated.
   • Dual-port: select storage based on a dual-port memory.
   • Single-port: select storage based on a single-port memory. The FIFO must be configured for either read-priority or write-priority as this determines which operation occurs when both operations are valid.
3. Build and test options
   • Build options: Build the FIFO; or build the FIFO and testbench; or build the FIFO and testbench and run the simulation using the Icarus Verilog simulator.
   • Sim cycles: The number of clock cycles used when testing the FIFO in simulation.
4. Actions
   • Build: Build the FIFO according to the specification. Build and run the testbench depending on the build options.
   • Clean: Delete generated files for the specified FIFO.
   • Reset: Reset the FIFO configuration to the initial blank settings.
   • Quit: Quit using Fifofum.
5. Status
   • Black: display the current FIFO specification.
   • Red: describe an error in the FIFO specification.

Building FIFOs using Make

For example, the following rule can be extracted from the example.make, where example is a low-power, synchronous, 32-by-8, flip-flop-based FIFO, with the optional rd_empty output:

example.v: fff_fifo.plv example.make
  prepro -r '#$$' -r '<#;>' -r '>#;>' -r '#[;]#' -o $@ $< ++ example:fflp32x8e +fff_gate

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